EDN

Low-cost resistive probe helps to accurately measure fast rise/fall ADC sampling clock

This usually means that a sampling clock with a relatively fast edge and good signal integrity is required to obtain maximum performance from the ADC. A sampling clock of 50 MHz is required in one of ...
EDN

Practical clocking considerations for high-speed ADC design

Among many deliberations when designing with high-speed analog-to-digital converters (ADCs), the effect of the ADC’s sampling clock is paramount to meeting specific design requirements. There are ...
Electronic Design

ADC Performance: What’s Jitter Got To Do With It?

Meeting the demanding performance requirements of today’s system-on-a-chip (SoC) applications, whether in high-data-rate telecom systems or high-quality audio and video equipment, requires extensive ...
Electronic Design

CTSD Precision ADCs (Part 5): Digital-Data-Interface Simplification with ASRC

Requirements for different types of sample rates. Conversion techniques for these different sample rates. Synchronous and asynchronous sample-rate conversion. This article starts with an overview of ...