Increased integration with nanometer processes is resulting in some devices that are using hundreds of small memory blocks distributed throughout the design. Memory BIST can be used to apply standard ...

As integrated circuits accommodate ever more transistors, the number of test vectors needed to test logic ICs rises dramatically. Design-automation companies are pursuing two design-for-test (DFT) ...

Reusable cores are a crucial component in creating system-on-chip (SoC) designs on time and efficiently. These intellectual property (IP) blocks enable SoC designers to quickly construct highly ...

Monitoring the health of a chip post-manufacturing, including how it is aging and performing over time, is becoming much more important as ICs make their way into safety-critical applications such as ...

Logic BIST Capability Slashes Test Costs By fortifying the DFT Compiler with deterministic logic built-in self-test (BIST) capabilities, the SoCBIST add-on module significantly cuts test cost by ...

Histogram-based BIST techniques harness on-chip resources to reduce test times and cost while keeping pace with increased circuit complexity. As the integration between digital and analog circuitry in ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to ...

It should come as no surprise that Moore's Law of regularly doubling chip capacity is having an impact on automatic test equipment (ATE) for ICs. ATE, of course, applies patterns of signals and checks ...