Electronic Design

Graph-Based Test-Synthesis Tool Creates Verification Plans

The complexity of today's system-on-a-chip designs creates serious verification challenges in various respects. It's increasingly difficult to write an effective and comprehensive verification plan.
Semiconductor Engineering

Advanced Design Debug Demands Integrated Verification Management

Design verification has been the dominant portion of chip development for years, and the challenges grow bigger every day. Single dies continue to grow in transistor count and complexity. Advanced ...
EDN

From specs to verification plans, by Relay

SANTA CRUZ, Calif. — As a functional-verification consultant, Steve Burchfiel once had to construct a verification plan from hundreds of pages of continually changing specifications. Convinced that ...
Semiconductor Engineering

LLM-based Agentic Framework Automating HW Security Threat Modeling And Test Plan Generation (U. of Florida)

A new technical paper titled “ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification” was published by researchers at University of Florida. “Current ...