One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.

[John] wanted a project to help him learn more about FPGAs. So he started with his wooden clock — made with an Arduino — and ported it over to a Lattice FPGA using Icestorm. What’s nice is that he ...

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...

Clock domain crossings are significant sources of field system failures. Despite this fact, designs continue to be released without fully verified CDCs. A false sense of security resulting from ...

Over a few short years, FPGA technology has advanced significantly. These devices have become extremely complex. FPGA blocks continue to maintain the phase-locked loop (PLL) technology capable of ...

Californian start-up Achronix has revealed details of its 1.5GHz asynchronous FPGA, which includes 10.3Gbit/s serialiser/deserialisers (serdes). “We get our speed from the underlying silicon ...

A few years ago the market was rife with deep learning chip startups aiming at AI training. This, however, is the year of the inference ASIC. But with millions invested in taping out a new chip in an ...

Histograms are often useful tools for analyzing digital data. To get reliable results from a histogram, though, you must collect large amounts of data, often with 100,000 to 1 million points. If you ...