EDN

PCIe 5.0 testing ensures accurate BER analysis

The release of the PCIe 5.0 specification earlier this year by the PCI-SIG was welcomed by designers of emerging applications such as artificial intelligence (AI), as well as engineers responsible for ...
Semiconductor Engineering

Sabnam Sahoo

The PCIe specification has given a specific Link Training and Status State Machine (LTSSM) state named Loopback, which is intended for test and fault isolation use. Basically, it gives a mechanism ...
TweakTown

Cadence teases PCIe 7.0 hitting 128GT/s with optical PCIe connections, successor to CopprLink

Cadence stole the show recently at the PCI-SIG DevCon 2024 event, and in honor of the 32nd anniversary of the PCI-SIG Developer's Conference, Cadence announced a complete PCIe 7.0 IP solution for HPC ...
Business Wire

Menlo Micro Introduces World’s First 64 Gbps Fully Integrated Loopback Solution for High-Speed Data Connectivity

IRVINE, Calif.--(BUSINESS WIRE)--DesignCon - Menlo Microsystems, Inc. (Menlo Micro), the company responsible for bringing to market the greatest electronic component innovation since the transistor ...
Electronic Design

Agilent Introduces Solution for PCI Express 3.0 Receiver Characterization

January 29, 2013. Agilent Technologies Inc. at DesignCon announced an enhanced solution for PCI Express 3.0 receiver characterization. The Agilent PCIe 3.0 receiver characterization solution provides ...
EDN

Switch enables high-speed digital loopback testing

Menlo Micro’s MM5620 dual DP3T switch operates from DC to 20 GHz, delivering up to 64 Gbps (64 GT/s) while maintaining high data signal integrity. This fully integrated system-in-package (SiP) permits ...