The paper presents the complete process of running/checking performance of high-speed interfaces (GHz/DDRs) in the mix mode (RTL+Spice) AMS verification. By inserting the abutted IO lump rail ...

As FPGA designers strive to achieve higher performance while meeting critical timing margins, one consistently vexing performance bottleneck is the memory interface. Today's more advanced FPGAs ...

The Virtex-II SiberBridge, a product jointly developed by the company and Xilinx, is a register transfer level (RTL) reference design that provides a high-performance interface between a 32-bit host ...

The GME product offering includes software, firmware and RTL and utilizes a common API and common RTL interface to facilitate platform portability. MoSys announced that its Graph Memory Engine (GME) ...

OSCI has recently published their TLM-2.0 technology which provides for interoperability between SystemC models of electronic components whose primary interfaces are memorymapped busses. This is a ...

The hardware/software interface (HSI) is where system-on-chip (SoC) software defines the connections between the software and the underlying hardware. Maintaining a precise, synchronized HSI across ...

What if a designer could simply use a GUI to input the memory system parameters and generate RTL code for use in an FPGA without writing it from scratch? As FPGA designers strive to achieve higher ...