Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
EDN

SoC design: What’s next for NoCs?

Today’s high-end system-on-chips (SoCs) rely heavily on sophisticated network-on-chip (NoC) technology to achieve performance and scalability. As the demands of artificial intelligence (AI), ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...
Semiconductor Engineering

Streamlining SoC Design With Advanced IP And Integration Solutions

As system-on-chip (SoC) complexity grows, so does the necessity for products that seamlessly connect IP and streamline integration processes, minimize manual errors, and enhance productivity. The ...
EDN

System-on-chip (SoC) design is all about IP management

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual ...
Business Wire

Intel Foundry and Arm Announce Multigeneration Collaboration on Leading-Edge SoC Design

SANTA CLARA, Calif. & CAMBRIDGE, England--(BUSINESS WIRE)--Intel Foundry Services (IFS) and Arm today announced a multigeneration agreement to enable chip designers to build low-power compute ...
Electronic Design

Predictive SoC Floorplanning Using Artificial Intelligence

Pain points of the existing floorplan designing process. How artificial intelligence can optimize this process to reduce the time taken from weeks to just hours. Potential applications of expanding ...