EDN

Implementing floating-point DSP on FPGAs

For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while ...
Design-Reuse

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
Design-Reuse

Start-up OptNgn Offers a Floating Point VHDL Library as Open Source

Portland, Oregon -- April 16, 2008-- OptNgn today announced that it is offering a floating point VHDL library under the GPLv3 Open Source License. FPGA designers can now save months of coding and ...
EDN

Fixed vs. floating point: a surprisingly hard choice

[Editor's note: For an intro to floating-point math, see Tutorial: Floating-point arithmetic on FPGAs. For an intro to fixed-point math, see Fixed-Point DSP and Algorithm Implementation.] The ...
The Next Platform

FPGAs Held Back in HPC, But Hope on the Horizon

The accelerator story for top supercomputers is a strong one, starting with GPUs, which were snapped in as coprocessors on some of the world’s largest systems over the last five years. Since then, ...
Machine Design

FPGAs put PLCs in motion

The quest for better throughput, faster changeover times, and less waste and downtimes has made machine-automation systems more complicated. Besides handling logic or process controls, systems today ...